This invention relates to integrated circuit and microelectromechanical systems (MEMS) devices. More particularly, this invention relates to the formation of vias in wafers on which the integrated circuits and MEMS devices may be fabricated.
Microelectromechanical systems (MEMS) are very small moveable structures made on a substrate using lithographic processing techniques, such as those used to manufacture semiconductor devices. MEMS devices may be moveable actuators, sensors, valves, pistons, or switches, for example, with characteristic dimensions of a few microns to hundreds of microns. One example of a MEMS device is a microfabricated cantilevered beam, which may be used to switch electrical signals. Because of its small size and fragile structure, the movable cantilever may be enclosed in a cavity to protect it and to allow its operation in an evacuated environment. Therefore, upon fabrication of the moveable structure on a wafer, (device wafer) the device wafer may be mated with a lid wafer, in which depressions have been formed to allow clearance for the structure and its movement. To maintain the vacuum over the lifetime of the device, a getter material may also be enclosed in the device cavity upon sealing the lid wafer against the device wafer.
In order to control such a microfabricated switch, electrical access must be provided that allows power and signals to be transmitted to and from the switch. Vias are typically formed in at least one of the wafers to provide this access. If the switch is for high frequency signals, it may also be important to design the vias such that their electrical effects on the signals are minimized or at least known and understood.
Accordingly, electrical vias allow electrical access to electronic devices or microelectromechanical systems (MEMS) within a package or in a circuit. In order to continually reduce the cost of such packages and circuits, the packing density of devices within the packages and circuits has been continually increased. In order to support the increase in packing density, the pitch between electrical vias for the devices has also continued to shrink. As a consequence, there is a desire to form vias of increasingly large aspect ratio, that is, the vias are tending to become increasingly long and narrow. Furthermore increased packing density requires that the placement tolerance of the vias be tightly controlled, since increased placement uncertainty requires the center to center separation to be increased to avoid inadvertent shorting of adjacent vias.
Long, narrow vias are often created by plating a conductive material into a hole formed in a substrate. A hole may be created in a substrate by a directional material removal process such as reactive ion etching (RIE). A seed layer may then be deposited conformally over the etched surface, to provide a conductive layer to attract the plating material from the plating bath.
However, when using this approach, the plating material in the bath has a tendency to be increasingly depleted down the depth of the hole. This will cause the plating rate to be higher at the top and near zero at the bottom, resulting in pinch-off at the top. Since the aperture to the via has become closed, pinched off, the plating bath no longer circulates and the confined bath within the hole is exhausted of its plating species. Plating into the hole will then cease, and a void is formed beneath the point of closure of the via aperture. Since these problems worsen as the via becomes longer and narrower, this approach becomes increasingly difficult for long, narrow vias. Specialized bath chemistries have been developed that reduce the negative effects cited above, but they can be expensive and are difficult to control.
Another known method for making vias is to use an anisotropic etch to form the holes with sloping sidewalls, and to deposit the conductive material on the sloped walls of the holes. However, this method often results in conductive material having non-uniform thickness, and the heat conduction in the thin deposited layer is relatively poor. The aspect ratio must also remain near 1:2 (width=2× depth), further limiting the density of the vias.
Each of these approaches involves the removal of substrate material in the hole to form the via, and the filling of this hole with a conductive material. The hole may be made by, for example, the methods described above and then filled by electroplating gold or copper. Because of the aforementioned problems with these approaches, such methods generally limit the aspect ratio of the via formed, and are also applicable only to conductive substrates.
Therefore, a need exists for a methodology which can form vias with high aspect ratio, and in variety of material substrates.